TRANSMISSION // 2611.13931v1

An AI-guided approach to balancing chip speed and power

Source published

TAPCO-G combines a language model that adapts optimization rules with graph-based estimates of how cell changes affect circuit timing and power. In tests on eight ASAP7 benchmark designs, it produced placement-legal, logic-equivalent results and scored higher than CERBERUS on all eight. Its average score advantage over an earlier system, TAPCO, was reported on the four designs where TAPCO produced valid results. These are benchmark findings reported in an arXiv preprint.

AI-generated conceptual illustration for An AI-guided approach to balancing chip speed and power
AI-generated conceptual illustration; not documentary evidence.

Making a chip faster can also increase its power use—or affect the timing of other parts of the circuit. TAPCO-G aims to navigate those trade-offs by pairing language-model-guided changes to an optimizer’s strategy with estimates grounded in circuit timing data.

A small change to a computer chip can have consequences beyond the component being changed. Replacing a logic cell with a faster one may improve a critical signal path, but it can also place a heavier electrical load on the cell driving it. The change may increase power or reduce timing margin elsewhere. The challenge is to improve timing and power while preserving the circuit’s layout legality and logic.

The paper introduces TAPCO-G, a software framework for making these trade-offs after a chip’s components have been placed. Its central question is whether an optimizer can make better design-specific decisions by adapting its repair strategy and estimating the effects of individual cell changes in greater detail.

Two levels of decision-making

TAPCO-G has an outer loop and an inner loop. In the outer loop, a large language model (LLM) uses feedback from optimization runs—including timing, power and physical-design diagnostics—to suggest changes to tool settings or to the executable rules that schedule repairs. If settings changes stop improving the result, the system can revise the repair policy itself, such as how it prioritizes timing problems or decides whether to keep a partial improvement.

The LLM does not determine on its own whether a specific cell replacement will help. The authors say language models cannot reliably estimate the detailed electrical effects of a change across a circuit. That is the inner loop’s role. It represents timing relationships as a graph, starts from a static timing analysis snapshot, estimates how a candidate replacement changes delay—including added load on upstream cells—and propagates those changes to affected timing endpoints. It also screens candidates for potential power effects before selected changes are tested with physical-design tools.

In short, the language model proposes strategy changes, while circuit-based estimates and tool evaluations assess candidate actions. The system checks that retained designs meet placement constraints and pass formal logic-equivalence tests, which verify that a transformed circuit still implements the same logic.

What the benchmarks showed

The researchers tested TAPCO-G on eight designs from the MLCAD 2026 Contest benchmark suite, using the ASAP7 predictive 7-nanometer technology. The designs vary in size and structure, and some include large memory blocks. The authors report placement-legal, logic-equivalent implementations for all eight.

On the paper’s quality-score measure, TAPCO-G scored higher than CERBERUS, the contest-winning system used for comparison, on all eight designs. Its mean score was 46.644, compared with 41.128 for CERBERUS, a reported average difference of 5.516 points. The paper also reports an average advantage of 21.648 points over TAPCO, an earlier version of the authors’ system—but this comparison covers only the four designs where TAPCO produced valid final implementations.

The authors also conducted 77 individual cell-replacement probes on two designs, AES and NVDLA-M. They applied proposed changes, measured their effects with timing and power analysis, and restored the original design state. The paper compares several prediction approaches: graph propagation without driver-load coupling and the full model both had higher sign accuracy than a local estimator in these probes. However, the full model’s mean absolute error was slightly higher than graph propagation without load coupling on AES, and higher on NVDLA-M. Thus, the probe results do not show that adding driver-load coupling reduced prediction error in every case.

Reading the results

The reported quality score combines timing, power and physical-design penalties using specified weights. The score differences therefore describe performance under the paper’s evaluation measure. They are not a direct measure of improvement under every possible set of design priorities.

The findings concern these eight ASAP7 benchmark designs and the evaluation setup described in the paper. The source is an arXiv preprint; the supplied materials do not establish whether it has undergone peer review. The results show how TAPCO-G performed in the reported experiments, while broader conclusions about its use beyond those tests are not established by this evidence.

Reviewed cross-references

These connections were reviewed by a model, not independently fact-checked by a human. Similarity does not imply agreement; consult the original papers and the evidence below.

  • ChipOmni uses engineering checks to guide AI chip design

    Shared method: Both frameworks use feedback from external engineering tools to guide iterative revisions: TAPCO-G uses physical-design results to adapt optimizer settings and repair policies, while ChipOmni uses tool diagnostics to refine designs across EDA tasks. This is a shared closed-loop approach, not evidence that their methods or outcomes are equivalent; TAPCO-G focuses on post-placement timing and power, whereas ChipOmni spans heterogeneous design tasks.

    Model review: · openai-codex/gpt-6-luna

    Evidence and provenance

    Selected excerpts, not complete papers. PDF extraction can omit figures or damage equations, tables and reading order; sources may be preprints.

    • 2611.13931v1 — Original paper

      Excerpt reference: static/papers/2611.13931v1.md:230-296
      Basis: Paper text
      Source SHA-256: ddfcb25aa4bd9577f1b00497737a31f354169e11a6c3c70733cc1b5bdbbc5d56

    • 2611.13020v1 — Original paper

      Excerpt reference: static/papers/2611.13020v1.md:194-269
      Basis: Paper text
      Source SHA-256: c8516f423b179834bf3d3b6ab91c10df4b294f68a28e4477ee1362b69f1a4c03

Automatically matched by shared topic keywords. These links do not imply that the sources agree or establish a consensus.