Can AI agents improve chip designs after synthesis has done its work?

A hardware design can be expressed as register-transfer-level code, or RTL: a description of how data moves and changes across clock cycles. Synthesis software turns that description into a circuit implementation. The tools already simplify and reorganize logic, so an RTL rewrite that looks clever in code may offer no benefit after synthesis. The central question in this paper is therefore practical: what optimization opportunities remain after strong synthesis tools have done their work?

The authors connect that question to a broader challenge in electronic design automation (EDA): how to evaluate AI systems on realistic hardware tasks, and how to make them use engineering tools and feedback rather than judge their output by appearance alone.

Three connected directions

First, the paper discusses two ways to benchmark RTL optimization. In a reference-based test, a candidate is compared with a known, human-optimized design. In an open-ended test, an agent starts with original human-written RTL and must find improvements without being given a target implementation. Both approaches assess whether the design still works and how it performs after synthesis. The paper argues that benchmarks should use realistic synthesis and verification workflows, since weak tools or artificially degraded starting code can make apparent gains misleading.

Second, the authors present Dr. RTL, a multi-agent system that analyzes timing reports, proposes RTL rewrites, and evaluates candidates using commercial synthesis and sequential-equivalence checking. That formal check tests whether a revised design preserves the original sequential behavior. The system also records which transformations worked under which circuit conditions, then stores these as reusable “skills” for later searches. This is experience reuse, not a claim that the underlying language model changes its parameters.

In experiments on 20 human-written designs, the authors report average improvements of 21.3% in worst negative slack (WNS) and 16.9% in total negative slack (TNS), alongside a 5.8% reduction in cell area relative to the commercial synthesis baseline. WNS and TNS describe timing violations; the reported improvements mean reductions in those violations. Nine designs improved timing and area together, and the average sequential-equivalence pass rate was 86%. That pass rate is important context: the reported results are not equivalent to saying every generated candidate was verified as correct.

Third, the paper explores optimization of synthesis itself. One experiment uses an agent to tune scripts for a commercial synthesis tool. Across eight designs, the authors report average WNS and TNS improvements of 7.4% and 11.1%, with 1.6% average area overhead. A second experiment evolves executable algorithms in an open-source synthesis flow. Across eight designs, it reports average reductions of 10.6% in area, 9.1% in delay, and 18.7% in area–delay product; seven of the eight designs improved in both area and delay.

What the results do—and do not—show

These experiments suggest that implementation feedback can help agents find changes that code inspection alone might miss. They also illustrate why correctness checks matter: a faster circuit is not useful if it no longer behaves as required. But the evidence is bounded. The RTL study uses 20 designs, and each synthesis-optimization experiment uses eight. The reported averages do not guarantee that the same gains would appear across other circuits, tools, technology libraries, constraints, or design teams. The RTL evaluation excludes power because reliable estimates depend on workload-specific switching activity, so it does not establish improvements across all aspects of power, performance, and area.

The paper is framed as an invited contribution presenting research directions and recent progress, as well as a future vision for joint optimization of architecture, RTL, and EDA algorithms. Its cross-layer, self-improving design automation is a proposal for further work, not a demonstrated end-to-end system in these experiments. The supplied source is a paper-text extraction associated with an arXiv preprint; extracted tables and formatting can be imperfect, and the source material alone does not establish independent replication or peer-review status. The results are best read as evidence that these approaches merit testing—not as proof that autonomous agents can yet optimize arbitrary chip designs reliably.