For silicon quantum memory, the route can matter as much as the circuit

Protecting quantum information requires repeatedly checking for errors without directly reading out the information being protected. Some promising error-correcting codes reduce the number of data qubits needed, but demand checks involving qubits far apart on a chip. How should a silicon processor connect them?

In a preprint, William Chow and Jonathan Baugh compare moving a helper electron with distributing entangled electron pairs. Their simulations reveal a consequential complication: an apparent advantage of the more elaborate circuit largely disappears when the simpler one gets a better physical layout.

Three ways to perform a check

A logical qubit stores information collectively across physical qubits. Quantum low-density parity-check, or qLDPC, codes use sparse checks: each involves a limited subset of the data. The measurement results form a syndrome, which classical software uses to infer errors.

The authors study two bivariate-bicycle qLDPC codes. The larger, called the Gross code, encodes twelve logical qubits in 144 data qubits. Those data qubits are not the entire hardware inventory: helper electrons, storage dots, readout facilities and transport lanes are also required.

One approach uses CAbLECAR, an existing scheduler that routes an ancilla—a helper qubit—between the data qubits participating in each check. In silicon, this means physically shuttling an electron whose spin carries the ancilla state.

The researchers propose two alternatives on a network of nodes connected by electron-shuttling lanes. Both distribute spin singlets, entangled pairs prepared locally before their members are transported apart.

One circuit combines these resources into a six-qubit GHZ state, a shared entangled ancilla whose components interact with individual data qubits. The other teleports an ancilla state between distant sites, using distributed singlets and measurement records. It transfers quantum information, not the electron itself. Neither approach eliminates transport noise: errors acquired by the distributed pairs can still affect subsequent checks.

Changing the map changes the winner

The team constructed schedules accounting for shared lanes and finite node resources, then simulated noisy memory circuits using Stim. A classical decoder inferred errors from repeated measurements. They tested transport that causes phase errors alone, and transport that additionally flips spins at two assumed relative frequencies.

Against CAbLECAR on its original layout, teleportation can win when transport includes enough spin flips. A fault on a moving ancilla can spread to several data qubits through subsequent interactions. Distributing entanglement before touching the data can limit that propagation, although it requires extra gates and measurements.

But the comparison initially changed both the circuit and the positions of the data qubits. Running CAbLECAR on the proposed node lattice shortened the Gross code’s mean scheduled ancilla route from 350 to 153 micrometres. In the sampled regimes with transport bit flips, its logical error rate improved by up to approximately fiftyfold relative to its original layout.

At the baseline hardware parameters, direct transport on that lattice then had a lower logical error rate than either singlet-based circuit at every sampled Gross-code point. The result is not a universal rejection of entanglement; it shows how strongly geometry can influence a circuit comparison.

Shortest is not always safest

The order of interactions matters too. An ancilla fault can create a correlated error across whichever data qubits it encounters afterwards. Changing the visit order changes those error patterns, even when the available operations are otherwise equivalent.

Fixing the visit order to that chosen on CAbLECAR’s original layout removed a small low-noise penalty seen with the new layout’s route-optimized order. However, it also lengthened routes and worsened performance when transport noise was stronger. Minimizing distance and limiting harmful error propagation are different scheduling objectives.

Extra protection has similarly conditional benefits. Checking singlets at their source improved both entanglement-based circuits, but could not catch errors introduced later. Phase purification, which consumes additional pairs and operations to check phase-error parity, worsened teleportation throughout the sampled unsaturated range. For the GHZ circuit, it helped only above a noise-dependent crossover.

A conditional opening for entanglement

Better local operations changed the comparison. With transport spin-flip probability one-third of its phase-flip probability, the verified, purified GHZ circuit overtook direct transport when the two-qubit gate and underlying measurement error probabilities were lowered together below roughly 0.0004–0.0005. That crossover was interpolated from simulations, not measured on hardware.

These are modeled memories, not a demonstrated processor. The comparison retains implementation differences, including additional readout gates in the singlet circuits and different scheduler constraints. Source verification also has optimistic baseline assumptions, with less favorable cases explored separately.

Finally, the reported logical error metric describes a twelve-qubit block per effective correction round. Round durations differ, so it does not alone establish which design preserves information best for a fixed elapsed time. The practical lesson is narrower: judge the complete layout, schedule and error propagation—not merely the elegance of the entangled resource.