TRANSMISSION // 2611.12833v1
GARI++ splits quantum error correction into a fast first pass and a smaller cleanup
Source published
A two-stage decoder reports competitive accuracy across three quantum error-correcting code families. Its first stage often finishes the job and otherwise leaves a smaller problem for another decoder, but the reported hardware and CPU timings do not establish complete real-time system performance.

Quantum error correction needs classical software and hardware to interpret error signals quickly enough to keep pace with a quantum processor. In a November 9, 2026 preprint, Arshpreet Singh Maan and colleagues present GARI++, a decoding pipeline that preserves useful partial work instead of starting over when its first attempt does not finish.
Turning error signals into corrections
Quantum error-correcting codes protect information by spreading it across physical qubits. Repeated checks produce a pattern of detection events, called a syndrome. A classical decoder must infer a correction from that pattern. Matching the observed checks is necessary, but it does not guarantee that the protected logical information has survived.
The challenge is both accuracy and speed. Larger codes can provide stronger protection, but interpreting their error signals can require more computation. Different code families also produce different decoding structures, making a single broadly useful approach difficult.
GARI++ addresses this with two stages: a message-passing decoder called GARI, followed, only when needed, by a decoder suited to the particular code family. Unlike ensemble approaches, it does not combine multiple decoding attempts to obtain its reported accuracy.
Keep the useful partial answer
GARI exchanges numerical messages between nodes representing possible errors and parity checks. These messages update estimates of which errors occurred and how strongly the evidence favors them. Its normalized min-sum algorithm simplifies those updates for efficient implementation.
The underlying graph is transformed to handle correlations between error components while removing certain short loops that impede message passing. Updates follow a hybrid schedule, including randomized serial processing of the original check subgraphs.
In the reported pipeline, GARI runs for at most seven iterations. For the Z-memory experiments studied, it stops when its proposed correction satisfies the Z-detector constraints—not necessarily every check in the augmented graph. That estimate is then accepted without a second stage.
If GARI does not finish, the pipeline retains its partial correction. The second decoder receives the remaining unexplained detection events, or residual syndrome, together with updated numerical weights derived from GARI’s confidence information. Its correction is combined with the saved partial answer.
The cleanup algorithm varies: Union-Find for surface codes, hypergraph Union-Find for bivariate bicycle codes, and Chromobius for color codes. Generality here therefore means a shared first-stage strategy with configurable cleanup, not one unchanged algorithm for every code.
Why the last iteration is not always best
More message-passing iterations do not necessarily produce a better handoff. In one distance-15 surface-code experiment, the average residual syndrome among still-unfinished cases reached a minimum around iteration four, then increased modestly.
GARI++ consequently uses what the authors call predictive pipelining. It saves an intermediate state when either the residual becomes smaller than in all previous iterations or a score based on confidence magnitudes exceeds that of the saved state. The selected state need not have the smallest residual: stronger confidence can also trigger replacement.
This is a selection rule, not a guarantee that the chosen intermediate answer will be best. Its purpose is to preserve useful information that later iterations might lose.
What the benchmarks show
The experiments primarily use simulated Z-memory circuits under uniform circuit-level depolarizing noise. Logical error rates include both cases completed by GARI and those requiring cleanup, and are reported per syndrome-extraction round.
For surface codes, GARI++ with Union-Find cleanup closely tracks correlated minimum-weight perfect matching across tested distances up to 71. For the tested bivariate bicycle codes, it improves on the specified BP-OSD reference and reports lower logical error rates than Relay-BP in the low-noise regime.
For superdense color codes, it improves on standalone Chromobius. The authors report an approximately tenfold reduction in logical error rate at distance 17 and physical error rate 0.001. These are benchmark-specific findings, not evidence of superiority under every noise model or operating condition.
Fast cleanup is not complete system latency
At physical error rate 0.001, mean residual Union-Find decoding time stays below one microsecond per round through surface-code distance 51 on a single Apple M2 core. Those measurements describe cleanup when invoked, with inputs prepared in advance. They exclude GARI processing, decoder construction, weight preparation and loading, and communication.
Separately, FPGA implementations of the GARI first stage fit surface-code distances 7 through 25 on one XCVU9P device. The paper reports average first-stage latencies per round ranging from 201 nanoseconds to 11.8 microseconds at that noise level. Larger implementations encounter routing and memory constraints.
The distinction matters: sub-microsecond cleanup does not demonstrate a sub-microsecond complete pipeline. Establishing that requires matched first-stage measurements, transfer costs, preparation overheads, and how often cleanup is invoked.
The work is an arXiv preprint, not established here as peer-reviewed. Its evidence supports a promising division of labor between programmable logic and a CPU, rather than a demonstrated end-to-end real-time quantum-computing system.
- quantum error correction
- GARI++
- quantum decoding
- message passing
- surface codes
- bivariate bicycle codes
- color codes
- FPGA
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