Atik uses one computing grid to accelerate two transformer bottlenecks

Transformer models repeatedly multiply matrices and calculate attention—the process that weights relationships between input elements. Atik, a hardware design described in a preprint by Ahmed Zeer and Erkan Uslu of Yildiz Technical University, tackles both operations with one shared computing grid. The reported gains are large, but their meaning depends on the baseline and on distinguishing directly measured kernels from projected model performance.

One grid, several jobs

Atik attaches to RocketChip, a RISC-V processor platform, through its custom-coprocessor interface. Ordinary C software supplies a descriptor containing tensor addresses, dimensions and the requested operation. The accelerator then handles moving data, dividing it into manageable tiles, performing calculations and writing results back.

Its central feature is a shared grid of multiply–accumulate units: arithmetic cells that multiply two numbers and add the result to a running total. Rather than building separate engines for matrix multiplication and attention, Atik reuses this grid for three tasks: ordinary matrix multiplication, computing attention scores, and combining values using attention weights.

The researchers evaluated grids containing four, 16 and 64 arithmetic cells, arranged as 2×2, 4×4 and 8×8 meshes. All three configurations use the same software interface and benchmark binaries.

Attention also needs softmax, a normalization step that turns scores into relative weights. Atik handles this through a streaming schedule, processing chunks while maintaining running maxima, normalization sums and output accumulators. It never stores the complete attention-score matrix.

That memory-saving schedule has a cost. When the output spans multiple column tiles, the design repeats score and softmax calculations for each tile. Sharing hardware and limiting working storage therefore involve extra computation and input traffic, not simply eliminating overhead.

What the measurements show

The authors evaluated the integrated hardware design using FireSim, a cycle-accurate simulation system accelerated by an FPGA on Amazon Web Services. The reported speedups compare target processor-cycle counts, not elapsed cloud execution times or measurements from a manufactured Atik chip.

The baseline was the same Rocket processor running BF16 software implementations, with the same memory system. Against that reference, the largest mesh achieved a peak speedup of 31.5 times for matrix multiplication and 225.8 times for attention. Aggregate speedups across the evaluated standalone cases were 31.0 and 181.7 times, respectively.

Those figures answer a specific question: how much does adding Atik help this scalar processor? Rocket lacks specialized vector or matrix hardware, and its software attention normalization is particularly expensive. The study does not establish an advantage over GPUs or vector processors.

Large relative gains also coexist with substantial unused arithmetic capacity. In a representative 64×64×64 matrix multiplication, Atik achieved about 2.83% of its mesh’s ideal arithmetic rate once data movement, conversion, control and writeback were included. Wider meshes generally helped larger problems more; smaller jobs amortized setup costs less effectively.

Model speedups are projections

The paper also reports aggregate speedups of 44.2 times for ViT, 77.1 times for TinyBERT and 32.3 times for GPT-2 prefill with the 8×8 configuration. These are hybrid projections for single-layer, workload-derived C models—not complete model runs on the accelerated hardware.

To calculate them, the researchers measured the full CPU workload, subtracted the CPU time spent on operations Atik replaces, and added directly measured accelerator-kernel cycles. The calculation assumes that the remaining software takes unchanged time.

That distinction matters: the projections combine hardware measurements with an accounting assumption, rather than demonstrating end-to-end acceleration of full deployed models. Autoregressive decoding with a key–value cache is outside the accelerated workload studied.

Numerical agreement is not model accuracy

Atik accepts and returns BF16 tensors, but internally converts values to fixed-point arithmetic. Softmax exponentiation and reciprocals use lookup tables. Its BF16 interface therefore does not imply bit-for-bit BF16 computation.

Across 137 logged FireSim test records, all checks passed their benchmark-specific tolerances, with no reported output mismatches under those checks. The largest logged absolute difference was 0.0625. These results establish numerical agreement for the benchmarks, not unchanged classification or language-model accuracy, nor accuracy without retraining.

The physical-design evidence is similarly preliminary. A standalone Sky130 study estimated accelerator area, with shared control costs spread across more arithmetic cells in larger meshes. It excluded the complete processor system and did not establish timing closure, power consumption or silicon performance.

The preprint’s contribution is thus a tested integration approach: one shared arithmetic mesh, a streaming attention schedule and a callable RISC-V interface. Full-model hardware runs, task-level accuracy evaluation and complete-chip timing and power measurements remain necessary to establish its broader practical value.