SAFTAC trains language models to design and repair analog circuits in simulation

Learning from electrical consequences

Analog circuits process signals that vary continuously, making their design a balancing act. Changing a transistor connection or component value can improve amplification while worsening bandwidth or power consumption. A plausible-looking circuit is therefore not enough: it must meet several electrical requirements together.

In an arXiv preprint posted on November 5, 2026, Junsheng Huang and colleagues introduce SAFTAC, short for Simulation-Augmented Fine-Tuning for Analog Circuit design. The framework adapts open-source language models to propose circuit structures and revise unsuccessful designs using diagnostic feedback.

The central idea is to make simulation part of training, rather than only a checking tool used around an otherwise unchanged model. The reported achievements are simulation-based design results, not demonstrations of manufactured chips.

Thousands of tasks, fewer underlying circuits

The researchers assembled 8,626 design tasks covering 10 circuit types, including amplifiers, current mirrors, mixers and delay cells. Each task includes a description, labeled connections, external loading conditions, target specifications, a simulation testbench and a reference netlist—the textual list of components and their connections.

Those thousands of tasks come from 114 unique reference netlists. Multiple tasks can therefore share an underlying circuit while asking for different performance targets. This distinction matters: the dataset’s task count is not a count of independently different circuit structures.

The construction pipeline combines existing circuit sources, language-model-generated descriptions, deterministic testbench scripts and simulation. Circuit experts check the source circuits, descriptions and testbenches. Bayesian optimization, a search method for choosing promising parameter settings, adjusts component sizes and values to establish feasible performance targets.

A curriculum followed by rewards

SAFTAC begins with three supervised training stages. First, the model learns to associate netlists with circuit functions. Next, it predicts missing components or connections. Finally, it learns to repair failed designs from simulation feedback, using demonstrations produced by a commercial teacher model.

Reinforcement fine-tuning then rewards the model according to an electrical validation pipeline. A proposed netlist must pass syntax, interface and connectivity checks. An external Bayesian optimizer searches component sizes and values for the fixed structure, and SPICE simulation measures its performance.

A circuit that fails the topology check receives a reward of minus one. A design meeting every target receives plus one; other outcomes receive zero. Training includes both fresh design generation and correction of failed designs.

Importantly, the language model is not doing every part of the engineering job. It proposes the circuit topology, while external optimization and simulation determine whether that structure can be sized to meet the requirements.

Better results on five circuit families

The main experiments adapt Qwen3-8B and evaluate five circuit families: common-gate amplifiers, common-source amplifiers, current mirrors, source followers and passive mixers. Each family has 64 test instances, with no overlap with training instances. The researchers sample eight rollouts per instance and report the fraction that succeed, called pass@1—not whether at least one of eight candidates works.

SAFTAC achieved an average initial-design success rate of 71.4%. Claude-Opus-4.7, the strongest closed-source comparator in this experiment, achieved 55.5%. That is a difference of 15.9 percentage points.

When a failed design could receive simulation feedback and one revision, SAFTAC’s overall success rate rose to 78.2%, compared with 70.4% for Claude-Opus-4.7: a 7.8-percentage-point advantage. A rollout counted as successful if either its initial or revised design passed.

The training recipe also improved other tested model backbones. These comparisons support the authors’ argument for specialized training, although they do not establish a universal ranking across circuit-design problems.

Transfer remains uneven

Tests on five circuit types excluded from training showed some transfer, but also substantial remaining difficulty. On active mixers, SAFTAC achieved 41.4% pass@1 with feedback, versus 1.6% for the base Qwen3-8B model. On differential single-ended amplifiers, however, SAFTAC reached only 3.1%.

The authors also identify computational cost as a limitation: repeated component sizing and SPICE simulations are expensive. Their main feedback evaluation allows only one revision, leaving longer repair sequences for future study.

The practical contribution is therefore a method for training models within a simulation-grounded workflow. It improves the odds that proposed circuits pass the specified checks, without eliminating the need for optimization, simulation or expert scrutiny.